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Altera_Forum
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15 years ago

How to constrain a source-synchronous desing?

Hi All, I am having problems setting up my sdc constraints for a source-synchronous interface that i have. The design is described as follows. --- The FPGA provide a reference clk(125Mhz) to a...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Rephrasing, to make sure I have it right, but you're saying the external delay should be the same regardless of whether they invert the clock or not. I completely agree. But he said he's failing timing(I think that was said). The analysis of that is partially "are my constraints correct" and if they are, then "what's going on inside the FPGA that can't meet my constraints". It's the latter part I'm moving on to, i.e. I believe the constraints are right(except maybe that -invert) and I want to see what's going on in the FPGA that causes it to fail timing.