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Altera_Forum
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15 years ago

How to constrain a source-synchronous desing?

Hi All, I am having problems setting up my sdc constraints for a source-synchronous interface that i have. The design is described as follows. --- The FPGA provide a reference clk(125Mhz) to a...
Altera_Forum's avatar
Altera_Forum
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15 years ago

I don't agree with that. Inverted or not, it is the output data clk and all delays are related to it.

if internal data clk is inverted out and as as long as the delay are related to output clk, the same argument below applies:

The data must not violate the receiving device's tSU of 1.2ns hence it can be delayed as maximum as that from next clk edge.

it must not violate tH of .2ns i.e. not be that early at the edge. So it is a straightforward SDR synchronous IF having 6.6ns valid window.

--tH--|------- valid window ------tSU|