How to constrain a source-synchronous desing?

It's an 8ns clock, and he said he inverts the clock going off chip. I assume the launch clock is not inverted. So if you draw the launch and latch clocks, they're both 8ns, but the launch is rising at 0ns, while the latch is rising at time 4ns. So it's really launch at time 0ns and latch at time 4ns, but it still results in a 4ns setup relationship.