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Altera_Forum
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15 years ago

How to constrain a source-synchronous desing?

Hi All, I am having problems setting up my sdc constraints for a source-synchronous interface that i have. The design is described as follows. --- The FPGA provide a reference clk(125Mhz) to a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The issue is not just 8 ns you read it as 10ns. but how do you divide time as launch 4ns, latch 4 ns and on what basis. Apologies but it sounds to me meaningless.