How to constrain a source-synchronous desing?

Yep. Hadn't had my coffee. I think I read 10-bit data as 10ns period. Anyway, with an 8ns period, launch at 4ns and latch at 8ns, that's a 4ns setup relationship. The external delay in your constraint is 2ns, which leaves 2ns for the FPGA, i.e. the data could be up to 2ns longer to get out of the FPGA than the clock and still meet setup timing. If matched, I believe this should be do-able. Would have to see the timing analysis to know why.