Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

How to constrain a source-synchronous desing?

Hi All, I am having problems setting up my sdc constraints for a source-synchronous interface that i have. The design is described as follows. --- The FPGA provide a reference clk(125Mhz) to a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

You have a 5ns setup relationship(10ns clk period with launch at 5ns and latch at 10ns), and

--- Quote End ---

Can't understand what you say at all.

tSU is 1.2ns, tH is .2ns, clk period is 8ns, its SDR interface I presume. I don't know from where you got your figures to overwrite my posts.