How to constrain a source-synchronous desing?

My undrstanding of output delays setting in TQ is:

Max = tSU + max data delay – min clk delay

Min = - tH + min data delay – max clk delay

Thus in your case it should be (ignoring board delays if clk delay = data delay):

max = 1.2

min = - .2

That gives a valid window of (your period - 1.2 - .2 = 6.6 ns) centred at 3.4ns from clk edge