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Altera_Forum
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15 years ago

How to constrain a source-synchronous desing?

Hi All, I am having problems setting up my sdc constraints for a source-synchronous interface that i have. The design is described as follows. --- The FPGA provide a reference clk(125Mhz) to a...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks for your response.

Your answer is helpful for me.

Would you please explain what condition the edge aligned will be applied and what condition the center-aligned aligned will be applied?

Thanks

Harris