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Altera_Forum
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15 years ago

How to constrain a source-synchronous desing?

Hi All, I am having problems setting up my sdc constraints for a source-synchronous interface that i have. The design is described as follows. --- The FPGA provide a reference clk(125Mhz) to a...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Haven't looked at the .zip, but does is the clock/data edge aligned or center-aligned coming from the AMCC chip? If it's edge-aligned, are you using a PLL to phase-shift the clock 90 degrees? (Constraints can change based on how it's implemented, naturally, so asking before writing out a quick example).