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Altera_Forum
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9 years ago

How to constrain a parallel bus from a PLL clock?

Hi. I have a couple of questions about the my design. Basically I have an FPGA which has a big data table which the values are readed and sent to an external DAC. The reading process and the DAC are ...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Hi Dirk,

Thank you for reply. I understand now. And related the skewed version for the DAC clock, which is the required skew? I guess that is required an offset equal to all the delay internal in the FPGA plus board delays? I guess that 3 latency cycles is not a problem, but it is necessary to get the relationship between the DAC clk and the data outputs from the FPGA.