How to constrain a parallel bus from a PLL clock?

Hi Frank,

the DSP multiplier with zero latency is the fastest you can implement in terms of propagation delay (zero latency refers to clock cycles, not path delay). But your goal is to process data @ 100MHz.The clock period is 10ns. The DSP Block needs about 5ns. The M9k needs also 5ns. Then you need margin for interconnect, tsu, tco.

This means you can't use M9k and DSP as a combinatorial path @ 100MHz.

You should do:

address generator -> FF -> ROM -> FF -> Multiplier -> FF -> Outputs

This setup is able to process Data at 100MHz datarate, with a latency of 3 clock cycles.

M9k and the DSP Blocks are able to use FFs as hardmacro. To get good IO Timing the last FFs should sit in the IO Buffer.

Dirk