How to constrain a parallel bus from a PLL clock?

Hi Frank,

specially a division in HDL takes a long time. You have to choose if you want to wait in clock cycles or in gate delay. In the altera cookbook there is a fast Radix 4 divider, that calculates 2 Bits within one clock cycle.That results in at least 16 clocks for a 64 / 32 division.

If you use the "zero latency" Version it will use combinatorial logic only. In my experience you result in a relativ low core frequency in the 10MHz range.

To make a division it is much faster to multiply with the inverse divisior. OK, this works only if the divisior is fix, or is changed slowly.

You may add the "set_multicycle_path" to your design, which helps tha timequest is not complaining. But the design won't work if you are still feed the divider with data @ 100MHz. That would be no solution.

To get a divider running with streamed data @ 100MHz i would suggest to create something like a pipelined divider. Or to multiply with the inverse divisior.

The dsp blocks will easily handle 16 by 16 bits @ 100MHz.