How to constrain a parallel bus from a PLL clock?

Hi Dirk,

I have some news. Regarding SDC constraints it seems work. I had an error in the logic whichs outputs the data. But now I have an additional general question. As in the previous case I have the ROM which outs the data @ 100 Mhz. But now I want to perform some calculations in the data before sendind it to the DAC. I am using the ALT_MULT and ALT_DIVIDE cores. It seems that is possible to use an option with zero latency (combinational logic only). After synthesis I get setup violations. As I guess a multiplication of 14 bits by 14 bits add a lot of combinatorial logic adding long delays. My question is if I can add the a "set_multicycle_path" between the register in order to fix this long delay. I tried to do this but in SignalTap II the signals are not the expected.