How to constrain a parallel bus from a PLL clock?

Hello Frank,

based on your reported Path the M9k is connected directly to the FPGA ports. You should check all corner cases that you match timing. Core to FPGA Pin tco timing (in timequest: port) may vary in my experiance more than 5, maybe 10 to 12ns over all corners.

And the DAC has also setup and hold times to match. DAC900 from TI has (ts=1.5 and th= 1ns). This setup and hold times are related to the PLL output, which comes out of the FPGA and has also a delay range.

Maybe you should consider to use FAST Output Registers, that are placed in the IO Buffer (verilog directive: (* useioff = 1 *)) and reclock the data with them. I am not shure, but maybe the Double Data IO Function (ddio) could be also used for your application. If alle the 14 Bits and the clock are generated the same way close in the IO Buffer you should get a good timematch.

Don't forget the max_skew_command and the report_max_skew. If i remember right Timequest doesn't report skew violations per default.

Dirk