How to constrain a parallel bus from a PLL clock?

Dear Alex,

Thank you for the guidance to understand tis issue. I followed the Altera wiki and some guides. I constrained the output as is adviced but I have setup violations.

I inserted the Timequest SDC cookbook lines:

create_clock -name CLOCK_50M -period 20.000 
 
create_generated_clock 
 -name CLOCK_DDS_100M 
 -multiply_by 2 
 -source }] 
  }] 
#  Specify the maximum external clock delay to the FPGA
set CLKs_max 0.5
#  Specify the minimum external clock delay to the FPGA
set CLKs_min 0.5
#  Specify the maximum external clock delay to the external device
set CLKd_max 0.5
#  Specify the minimum external clock delay to the external device
set CLKd_min 0.5
#  Specify the maximum setup time of the external device
set tSU 2
#  Specify the minimum setup time of the external device
set tH 1.5
#  Specify the maximum board delay
set BD_max 0.82
#  Specify the minimum board delay
set BD_min 0.657
#  Create the output maximum delay for the data output from the FPGA that accounts for all delays specified
set_output_delay -clock CLOCK_DDS_100M-max  }]
#  Create the output minimum delay for the data output from the FPGA that accounts for all delays specified
set_output_delay -clock CLOCK_DDS_100M-min  }]

Related the data send to the DAC is fixed. I instantiated a ROM initialized by a .mif file. The problem is a setup violation for each DAC line (each bit) I attached the report file for the DAC[7] signal.

I guess that the data can travel at 100 Mhz from the ROM output register to the output pin in less than 10 ns. For this I though in use a multicycle in order to allow 2 cycles to reach the output pin.