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Altera_Forum
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14 years ago

How to constrain a non-source-synchronous bus with certain data skew

Hi all,

How should I constrain a non-source-synchronous output bus with certain skew between different data bits?

Let's say, the FPGA outputs a 32-bit data bus to an external device. The data bus runs at 50MHz inside the FPGA, but there is no output clock associated with it. What we want to do is to constrain the output data bus to ensure that the skew between different data bits in the bus does not exceed some certain value (250ps, for example). How should we do this?

I know that for source-synchronous output, which has clock output together with the data bus, we can use

output delay max = latch - launch (setup) - skew

output delay min = latch - launch (hold) + skew

But I don't know whether this rule also applied to non-source-synchronous output. Should we create a 50MHz virtual clock and use the equations listed above to calculate the output delay? Or is there any other way to do it?

Thanks

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    How about treating it like an edge-aligned DDR output bus (whose clock changes at the same time as the data bits?). For example (and not checked for syntax errors): 

    
create_generated_clock -name clk_bus -source {<bit0_ff_clk_pin>} -divide_by 2 -phase 90 }]
set bus_outs  }]]
set skew 0.400
set_output_delay -clock  -max $skew $bus_outs
set_output_delay -clock  -max $skew -clock_fall $bus_outs -add_delay
set_output_delay -clock  -min  $bus_outs -add_delay
set_output_delay -clock  -min  -clock_fall $bus_outs -add_delay

    Increase $skew until it barely meets timing.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    How about treating it like an edge-aligned DDR output bus (whose clock changes at the same time as the data bits?). For example (and not checked for syntax errors): 

    
create_generated_clock -name clk_bus -source {<bit0_ff_clk_pin>} -divide_by 2 -phase 90 }]
set bus_outs  }]]
set skew 0.400
set_output_delay -clock  -max $skew $bus_outs
set_output_delay -clock  -max $skew -clock_fall $bus_outs -add_delay
set_output_delay -clock  -min  $bus_outs -add_delay
set_output_delay -clock  -min  -clock_fall $bus_outs -add_delay
    Increase $skew until it barely meets timing.

    --- Quote End ---

    Thanks. However I am not quite sure whether this kind of constraint will work. If look at Altera an433.pdf, it suggests that using the way you described to constrain input ports. For output ports, an433 gives a quite different delay calculation...

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    This constraint does work for source synchronous outputs. Try it and see what you get.