How to constrain a non-source-synchronous bus with certain data skew

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How about treating it like an edge-aligned DDR output bus (whose clock changes at the same time as the data bits?). For example (and not checked for syntax errors):

create_generated_clock -name clk_bus -source {<bit0_ff_clk_pin>} -divide_by 2 -phase 90 }]
set bus_outs  }]]
set skew 0.400
set_output_delay -clock  -max $skew $bus_outs
set_output_delay -clock  -max $skew -clock_fall $bus_outs -add_delay
set_output_delay -clock  -min  $bus_outs -add_delay
set_output_delay -clock  -min  -clock_fall $bus_outs -add_delay

Increase $skew until it barely meets timing.

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Thanks. However I am not quite sure whether this kind of constraint will work. If look at Altera an433.pdf, it suggests that using the way you described to constrain input ports. For output ports, an433 gives a quite different delay calculation...

Thanks.