Forum Discussion
JWrig25
Occasional Contributor
Occasional ContributorHow to configure the PCIe Hard IP block on a Stratix V GX FPGA Development Kit using Quartus.
I have been trying to configure the IP block for PCIe on my Stratix V GX FPGA and I was following along the steps in this document https://www.intel.com/content/dam/www/programmable/us/en/pdfs/litera...
BoonT_Intel
Frequent Contributor
Frequent ContributorHi Sir,
For the SV kit, you can use this reference design and see it fit correctly.
https://fpgacloud.intel.com/devstore/platform/14.0.0/Standard/an-690-pci-express-dma-reference-design-for-stratix-v-devices/
JWrig25Occasional Contributor
Occasional ContributorHi, I have tried to click on the documentation for that example but after I agree to the terms and conditions nothing happens. No files get downloaded. There doesn't seem to be any other relevant information on that site, I have tried the tutorial and that does not work either. I thought the issue might be my internet connection but I have tried two different wifi sources and the website does not load anything for either of them. Is there something I am missing? Thanks.
