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Altera_Forum's avatar
Altera_Forum
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17 years ago

how to compile a package in quartusII

Hi,

I want to build a project named "adder". And I would like to use two of my previous projects to built it,which I have been compiled before. Here I assumed the two named "h_adder.vhd" and "or_2.vhd". Then a problem comes to me. How to create a package using these two projects?And then how to add this package into my "adder" project? Need I compile the package?

Tks for replying

P.E.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You have to build a new project named "adder". You can use the New Project Wizard and follow the hints. I suggest you to use a folder named "adder" and put the vhd files in this folder.

    During the new project wizard you have to add all the vhdl files in the file list.

    Then you have to create a top-level design file (can be a bdf schematic or a top-level vhdl file) which will specify the connections between the two modules that you have designed before.

    After that you will have to compile the new project "adder" and you will have the desired result.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Logic from external sources can be used in a package only, if it's a VHDL subprogram, either procedure or function. Component code has to be added to the project as VHDL source.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    --- Quote Start ---

    You have to build a new project named "adder". You can use the New Project Wizard and follow the hints. I suggest you to use a folder named "adder" and put the vhd files in this folder.

    During the new project wizard you have to add all the vhdl files in the file list.

    Then you have to create a top-level design file (can be a bdf schematic or a top-level vhdl file) which will specify the connections between the two modules that you have designed before.

    After that you will have to compile the new project "adder" and you will have the desired result.

    --- Quote End ---

    Tks for your reply.I think I can get your idea.However,I would like to use a package to specify the connections between the two rather than a top-level design file.If that,what I need to do is just to state the package in my design file.

    So,could tell me how to create a package,specify the connection in the package,compile it and then make use of it in my file.

    Tks.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    If your files "h_adder.vhd" and "or_2.vhd" contain components then, as FvM says, they cannot be included in a package.

    You cannot use a package to specify connections between components, you must use a VHDL source file component