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Altera_Forum
Honored Contributor
17 years agoLogic from external sources can be used in a package only, if it's a VHDL subprogram, either procedure or function. Component code has to be added to the project as VHDL source.
Logic from external sources can be used in a package only, if it's a VHDL subprogram, either procedure or function. Component code has to be added to the project as VHDL source.