Forum Discussion
Altera_Forum
Honored Contributor
12 years agoUse a function containing a loop that maps the input std_logic_vector into your census_line type, i.e.,
function to_census_line (slv : in std_logic_vector) returns census_line is
variable result : census_line;
begin
for i in 0 to 15 loop
result(i) <= slv(8*i+7 downto i);
end loop;
return result;
end function;
This function needs to go after the census_line type definition. I just typed this directly into the forum, you'll have to debug any VHDL errors :) Cheers, Dave