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NuvKFC's avatar
NuvKFC
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1 year ago

How to apply set_disable_timing SDC command before synthesis?

I have a path, Cell|in to Cell|out, want to disable by using set_disable_timing like follows. set_disable_timing -from dataa to combout Cell After Fitter, I can find the signal in on the dataa, and...
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ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


Means that you possible to see node c after synthesis? Probably can include node c in sdc after synthesis. Or using wildcard.

I believe sdc constraints like set_disable_timing will be processed at timing analysis stage.


Thanks,

Regards,

Sheng


  • NuvKFC's avatar
    NuvKFC
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    1 year ago

    Thank you, ShengN, very, very, mhch.

    No, I get a problem. Sorry about that.

    I'm a Quartus GUI user.
    Before getting off work, I click start compilation. Then next day, I can check the result.

    However, "start compilation" button will continuous do Synthesis, Fitter, Timequest, and Assembler.

    The next day, I only can see the result that after Fitter.
    So, I only can find the "cell|datac" where is the node c location in the Chip Planner after Fitter.

    Could you please tell me how to find the specified node after Synthesis?.