Contributor
ContributorThank you, sstrell, very, very, much.
Yes, you are right.
However, the node A only work under that Test is 1 which is one kind of test mode.
On the FPGA, we don't verify that test mode.
So, I want to break the timing arc on the node A to reduce resource cost and compiler time.
I can't find a way to do that expect for modifying RTL code.
ContributorAnd there are the other case about output clock on the pad.
The PAD A have 2 functions.
One is the data path from Function A.
The other one is the clock path from Function B.
If I create a generated clock for CLK B on the PAD A, that clock will go into Function A.
So, Function A will have two clocks, the generated clock on the PAD A and PLL output.
However, the clock of Function A, the clock of Function B, and the generated clock on the PAD A are in the same clock domain.
I need take many many effort to set false path between the generated clock on the PAD A and the Function A.
So, I want to stop the clock propagating of the generated clock on the PAD A into the Function A.
Unfortunately, I don't know where is the Node C before synthesis when use the set_disable_timing command.
