Contributor
Super ContributorUsually timing analysis is performed from/to registers or ports, not for individual logic cells on the path. When you cut a logic cell, you cut the whole path. Why not simply specify a timing exception between pre-synthesis entities? What do you want to achieve?
ContributorThank you, FvM, very, very, mhuch.
My purpose is for ASIC verification.
The design's architecture is as follows picture.
There are 2 clocks that pass the mux logic which is controlled by test signal.
I want to break the timing on node A or the timing path from node A to mux|out.
Due to unsupported set_case_analysis command, I try to use set_disable_timing command to do this.
Unfortunately, I don't know that the node A is on the dataa, datab, datac, datad, datae, or dataf before synthesis.
And I had tried to set_false_path command, but it can't work on a clock path.
Ex. set_false_path -from PLL/clock -through mux|out. (The mux|out node is CLK in the above picture.)
