How to analyze the power of OpenCL code in Arria 10

All data from high-speed peripherals outside of the FPGA need to go through the high-speed transceivers inside the FPGA so that data width and signal frequency is adjusted to values that can be processed by the controllers inside the FPGA; this includes PCI-E, DDR memory, network ports, etc. I don't think you would be able to find any meaningful mapping between the way you write your kernel code and the breakdown of the power consumption.