Forum Discussion
AnandRaj_S_Intel
Regular Contributor
6 years agoHi Haseeb,
Yes, you have to include `(tick) in front of include statement.
`include "parameters.v" with quotation.
without quotation we may see Error (10096): Verilog HDL Compiler Directive error at top.v(1): incorrect use of predefined text macro "include" -- expected macro field ""filename""
Regards
Anand