Forum Discussion
CheepinC_altera
Regular Contributor
6 years agoIt would be great if you could share with me a simple test design QAR.
- gyuunyuu6 years ago
Contributor
The zip file contains following things:
- .vhd file for a custom Qsys component
- _hw.tcl file for item in (1)
- .qsys file of a system where (1) has been instantiated
- the generated simulation and synthesis files
If you look at the generated simulation and synthesis entity top level, you will find that it has no generics and only ports.
I can open Qsys and change the values of the generics. But, Qsys does not have option to provide access to these generics in the top level entity.
I can of course just modify the code by hand and add generics to the simulation and synthesis top level entities. But these shall be lost when the system is generated again.
In summary, the qsys_component.vhd has:
generic ( counter_max: integer range 15 to 65535 := 15; write_address: std_logic_vector(31 downto 0) := (others=>'0') );I want that the top level entity of Qsys system expose these as well. The top level entity is qsys_system.vhd.
- gyuunyuu6 years ago
Contributor
Dear cphan, I uploaded some files onto the forum yesterday, which you can use to understand the problem. Regards, Hassan Iqbal