Forum Discussion

Ruturaj_D_Intel's avatar
Ruturaj_D_Intel
Icon for New Contributor rankNew Contributor
6 years ago

How TimeQuest analyzes path though the latch?

I want to know if TimeQuest analyzes path through the latch. If there is latch in the design how do I make sure that timing gets analyzed by static timing analyzer. In my design I see that tool gives...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

I am sorry for the late response.

Timing Analyzer found latches across multiple look-up tables (LUTs), or latches that do not include an enable (e.g. SR latches). The Timing Analyzer does not support analyzing this latch implementation as a synchronous element, but treats these latches as a combinational loop.

It is recommended to design without the use of latches whenever possible. You have to implement these latches with registers using asynchronous load and data signals, or remove these latches from your design.

You may refer to Intel Quartus Prime Pro Deisgn Recommendation User Guide https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-recommendations.pdf (Chapter 1.5.3 Latches)

Please let me know if you have any questions.

Thanks.

  • Ruturaj_D_Intel's avatar
    Ruturaj_D_Intel
    Icon for New Contributor rankNew Contributor
    6 years ago
    Hi, Thank you for clarification. I do have one more follow up question; my understanding is that for timing analysis of latch as synchronous element, enable signal needs to be defined as latch. I could not find document describing this requirement and how to define clock on enable signal. Is there a doc which talks about how to define clock on enable signal for STA? Other question is regarding flop with asynchronous load; does Startix10 FPGA support implementation of flop with asynchronous load. Thanks, Ruturaj.