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The design was meeting timing when the utilization was around 80% - so I assume the violations now are due to the added logic (90%)
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Yes and no. If your design contains unnecessarily long paths, then you may be making the tool work hard to meet timing. If you can pipeline logic, then its generally a good idea to try that.
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And I am already working with the best speed grade. And none of the DDR constraints are ignored. FYI, I am working with Quartus-II 6.1 and classic timing analyser - cannot help these facts as its a legacy design!
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What feature of 6.1 is needed? You should be able to upgrade to the newest version of the tool that supports the device you are working with. If its a FLEX or ACEX you can use 9.0SP2.
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And when I reduced some logic (which was acceptable), the timing meets occasionally (now utilization is 84%). And when it fails, the violations are no more in DDR - each time a new part of the design in the 200 MHz domain fails to meet.
My feeling is, the device utilization is at its saturation point for timing closure.
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The tool is not very granular. It has to look at the design as a whole, if you have some poorly coded logic in one area of the design, then the tool does not account for that in its attempts to meet timing. Take a look at your code as a whole, not just the failing paths.
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So, am back to my question - how much violation can be safely waived?
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Can you control the clock source to the design, eg., via an external synthesizer or by using a PLL inside the device? If so, run a test that shows the hardware is all working, and then keep increasing the operating frequency. Once the design stops working, you'll have an idea of what your timing margin is. This is only a single sample test though, and by (bad) luck you might have the fastest version of the device you'll ever buy, so the results should be interpreted conservatively ;)
This test is easier to do with an external synthesizer since you can just program a new frequency. If using a PLL, you need to use a reconfigurable PLL, so that you are not changing timing (by resynthesizing the design with a new PLL setting).
Cheers,
Dave
Honored Contributor
