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The design was meeting timing when the utilization was around 80% - so I assume the violations now are due to the added logic (90%)
And I am already working with the best speed grade. And none of the DDR constraints are ignored. FYI, I am working with Quartus-II 6.1 and classic timing analyser - cannot help these facts as its a legacy design!
And when I reduced some logic (which was acceptable), the timing meets occasionally (now utilization is 84%). And when it fails, the violations are no more in DDR - each time a new part of the design in the 200 MHz domain fails to meet.
My feeling is, the device utilization is at its saturation point for timing closure.
So, am back to my question - how much violation can be safely waived?
Thanks,
Satish
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Ideally you need to pass timing. If it gets hard here is my approach:
Check failing path for any signals that have higher probability of failing . The idea is to see if you can improve on them.
revisit the code for any long paths.
check that some paths can be deconstrained
If after all it fails marginally then DSE can help as it may vary slack by some +/-10% or so.
If you have to live with negative slack then what matters is the signals involved and DVT (device,voltage,temp) variables and I don't see the relation to be linear but I better see some builds and test them in hardware directly.
Honored Contributor
