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There are 100 and 200 MHz domains in my design and violations are obviously in 200 MHz domain. I have tried DSE - but these violations are hard to close. The violations are inside DDR2 controller of Altera (it is encrypted, so no way I can try to fix them). To make matters worse, the device utilization is a whopping 90%.
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Have you tried reducing the logic usage - just to see if the errors clear? At least that would then confirm that the high utilization was leading to the DDR controller failing timing.
Does TimeQuest indicate any DDR constraints are being ignored or not matched? There are paths in the Altera IP that are supposed to be cut, but in some cases, I've seen the constraints ignored (in the PCIe IP if I recall correctly).
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Also, does it make sense to run DSE on a machine with 4GB RAM and i5 core processor on Windows 7 - I see it hang after 3 to 4 iterations.
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I've never had DSE produce anything useful.
I'd look into confirming that it is possible to get the DDR controller to meet timing with a reduced logic design, and then send the file(s) to Altera in a Service Request, eg., either two separate designs or a design with a generic that changes the resource utilization.
In parallel with that you could see if using a design partition helps, eg., restrict the placement of the DDR controller ... though I have not used this aspect of Quartus, so can't comment on the likelihood of success. I do know of Xilinx users that have had to resort to floor planning to squeeze that last ounce of performance out of their parts.
The other thing you can do is to try a couple of different speed grades - not because you should use a faster device, but to get a sense of how badly constrained the DDR controller is.
Cheers,
Dave
Honored Contributor
