How does TimeQuest Analysis determine Launch edge & Latch edge?

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...       	           
counter_clear_gen: process (IN_CLK, IN_STROBE)
   begin
       
...
   end process;
counter_operation:	process (IN_CLK, s_counter_clear, IN_STROBE)
	begin
...
	end process;

...

P.S. The IN_STROBE & IN_CLK are unrelated clocks.

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Any single process should have only one clock in the sensitivity list. Look at a VHDL book or the Quartus handbook for coding style recommendations. The handbook chapter and one suggested book are at http://www.alteraforum.com/forum/showthread.php?t=1025.