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Altera_Forum
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18 years ago

How does TimeQuest Analysis determine Launch edge & Latch edge?

I have to clocks generated from PLL. CLKA is 80Mhz, CLKB 100MHz. I noted that the launch edge is 10ns and latch edge is 12.5ns in setup time report from CLKB to CLKA. How does TimeQuest ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Do you mean that it is designer's responsibility to ensure that the circuit handles any clock domain crossing appropriately? And TimeQuest Analysis can't do anything helpful for asynchronous clock??