Honored ContributorI have a question regarding the compilation process.
Considering a multi-layer hierarchically hardware description, how does Quartus handle the compilation? Does it unwrap all layers and then compiles the complete circuit, or does it compile each entity as a subcircuit and than makes the connections between?
Honored ContributorIt goes through several processes
First, it converts all of your code to altera units, like altsyncram, adders, multipliers etc. then it maps all of these to luts and individual rams. then it places all these base units onto the die.Honored ContributorSo if I understand correctly, it is all flattened to a single hierachy level so to speak.
Honored ContributorBasically yes, but heirarchy information is kept so it is easy to navigate the technology map, and you can map a specific register all the way from source code onto the FPGA.
Honored Contributorit's clear, thanks
