How does Quartus handle flip flop with both async reset and set

Hi all,

I am implementing a FPGA prototype of an ASIC on Stratix-III FPGA.

I am having also async CLR and SET in my RTL (ASIC RTL). To keep the functionality I have to perform as less as possible RTL modifications on the ASIC RTL. I noticed that such stucture leads to combinational loops in the synthesis and long P&R compile time. I also suspect that many gated clocks are not converted due to such warnings.

Do you have any idea how to modify the RTL to keep the functionality as the ASIC RTL and prevent combinational loops?

Regards