How does Quartus handle flip flop with both async reset and set

The actual registers in these devices support asynchronous clear. To support asynchronous preset rather than clear, they do what's called NOT gate push back, which I never found to be the most obvious description of the process. Basically, they just invert the register's input and output, effectively changing the power-up state from GND to VCC. Now when you clear the register, it will behave like a preset.

If you want both clear and preset, then you need another asynchronous control signal. In the older families before Stratix III, you could use an aload. I guess this feature wasn't worth the bang for the buck, so to speak, because it was removed. The latch emulates it more or less satisfactorily but better to remove the requirement from a design entirely.