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So common sense tells me that this is a 32 bit counter - but is that an asynchronous or synchronous counter? In my schematic design, I just used simple ripple counters because I didn't need synchronous for a clock divider.
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Its a synchronous counter, because the addition occurs on the rising edge of the clock.
And can I stop you before you carry on down your asynchronous path - FPGAs are designed to be synchronous. Ripple counters, logic generated clocks etc are a bad idea inside an FPGA. The delays and skew in the clocks will be dependant on the P&R and also PVT. So what works one time may not work the next time you compile it, or when it gets hot etc. And you cannot perform timing analysis on an asynchronous design.
So it is highly recommended you use the same clock as much as possible and generate clock enables to divide any clock - not ripple counters or logic generated clocks.
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And does the software implement the above "+" sign as a counter or as a 32 bit adder with full carry look ahead? Would "cnt = cnt + 3'b101;" work? Mathematically speaking, adding 1 to a number is a counter, but electronically, adders are considerably more complicated and are going to suck up more LE's on the chip.
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It will be a 32 bit adder with full carry look ahead because thats what the code asked for - and how the FPGA is optimised. The luts in the FPGA all have a high speed carry chain exactly for this purpose.
And yes, cnt = cnt + 3'b101 would also work just fine, the same way, and probably just as fast as 1'b1.
With devices as they are now, logic is not usually the limiting factor in designs - the problems usually come with lack of RAMs, DSPs or routing resources.
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