How do I split a bus into individual signal lines?

I'll probably complete this design with schematics and then migrate each module to HDL one at a time. There are a lot of things I don't know about HDL. Take the following counter code (one of many from the other guy):

reg cnt;
always @(posedge clk)
	begin
		cnt = cnt + 1'b1;
	end

So common sense tells me that this is a 32 bit counter - but is that an asynchronous or synchronous counter? In my schematic design, I just used simple ripple counters because I didn't need synchronous for a clock divider.

And does the software implement the above "+" sign as a counter or as a 32 bit adder with full carry look ahead? Would "cnt = cnt + 3'b101;" work? Mathematically speaking, adding 1 to a number is a counter, but electronically, adders are considerably more complicated and are going to suck up more LE's on the chip.