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It does seem that a lot of people are going HDL.
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Since I started in FPGA land 10 years ago schematics were frowned upon.
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I like schematic design because its easy for me to debug. I can just look at it and tell what its doing and what's wrong. I'm sure other people can do the same with HDL, but not me. I know HDL has several advantages, but one thing I did notice is that the HDL version of my project (done by others) took about 4X as many LE's as my schematic version did. The schematic version consisted entirely of logic primitives and TTL blocks so I didn't do any intensive optimizing.
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This really comes down to the designer. Im sure it would work just as well in HDL as in schematic if it was done properly.
Im sure youre design was very clever and worked well, but would someone else have understood it? I have never seen a well commented schematic, and while I have seen some terrible code, I would rather work out whats going on from poorly commented code than a schematic. I have spent weeks trying to understand and fix someone elses terrible (and undocumented) schematics - they had links crossing all over the place, with named association spanning vast distances across pages. How am I meant to find a bug in that?
So - for me:
Pros:
- It can look neat at a higher level
Cons:
- Cannot be used with version control (you get no visualisation of changes over time)
- Cannot be directly simulated (you need a netlist or convert to HDL to simulate)
- Easily becomes a mess
- not easy to add comments
At the end of the day - without HDL knowledge, your job market is going to be severely limited, if not non-existant.
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