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BHunt11's avatar
BHunt11
Icon for New Contributor rankNew Contributor
5 years ago

How do I report powered-down transceivers and PLLs in Quartus Prime Standard?

I have an issue which looks like an xcvr_fpll_a10_0 may not be powered or is shut down. How can I confirm that all the PLLs are in fact powered on in Quartus?
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Unfortunately clkusr is a must requirement. clkusr provided clock to transceiver channel to perform power on calibration during FPGA power up stage before FPGA enter user mode.

In your case, the transceiver channel may already gone wild and malfunction during power up stage due to missing clock before you can perform any transceiver operation (be it loopback test or anything) after FPGA enter user mode.

So, I don't think it will works and whatever test result on transceiver is not reliable as well.

Thanks.

Regards,

dlim