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BHunt11's avatar
BHunt11
Icon for New Contributor rankNew Contributor
5 years ago

How do I report powered-down transceivers and PLLs in Quartus Prime Standard?

I have an issue which looks like an xcvr_fpll_a10_0 may not be powered or is shut down. How can I confirm that all the PLLs are in fact powered on in Quartus?
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

There is no special power control for fPLL.

By default fPLL is power on as long as user provide the FPGA power, PLL refclk source and fPLL is not in reset mode via "pll_powerdown" control from reset controller IP.

User can then check pll_locked signal and output clock frequency to ensure it's alive and behaving properly.

Thanks.

Regards,

dlim

  • BHunt11's avatar
    BHunt11
    Icon for New Contributor rankNew Contributor
    5 years ago

    I found my issue. I don't have the CLKUSR pin connected to a clock source so the transceiver is not completing calibration.

    Is there a way around using this external pin? Can I supply an internal clock source?