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sgadco's avatar
sgadco
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5 years ago
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How do I connect my CDPLK pin to the GCLK without the use of a clock control block in quartus ?

Hello, I am using the Cyclone 10 LP and Quartus Prime Standard Edition 18.1. I am using the Y6 pin(CDPCLK) for my FPGA_CLK signal. This clock signal has to be given as an input to the PLL. ...
  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    5 years ago

    Hi Aaron

    You are right. Clock control blocks that have inputs driven by dual-purpose clock I/O pins are not able to drive PLL inputs, which is the behavior of the CDPCLK pin. The PLL IP will not be able to take the CDPCLK as reference clock. PLL should always take clock input pin or GCLK driven by clock input pin as reference clock.

    Thanks.

    Eng Wei

GY_Intel's avatar
GY_Intel
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5 years ago

Hi, Please refer to the similar thread. Thanks

  • sgadco's avatar
    sgadco
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    5 years ago

    Hello,

    Can you post the link to the thread. I am unable to find any similar thread. Thanks

    • EngWei_O_Intel's avatar
      EngWei_O_Intel
      Icon for Frequent Contributor rankFrequent Contributor
      5 years ago

      Hi Aaron

      You are right. Clock control blocks that have inputs driven by dual-purpose clock I/O pins are not able to drive PLL inputs, which is the behavior of the CDPCLK pin. The PLL IP will not be able to take the CDPCLK as reference clock. PLL should always take clock input pin or GCLK driven by clock input pin as reference clock.

      Thanks.

      Eng Wei