New Contributor
Super ContributorI'm not sure why you don't want to use a particular resource, but you can force logic into resources you do want to use with Logic Lock regions in the Chip Planner. Draw shapes (rectangular by default; merge them together to make non-rectangular shapes) and assign logic from your design to a region. Then the Fitter is forced to place the logic in that region.
Be aware that if you have a very full design, this could cause no-fit or timing issues due to you forcing logic into specific locations, away from where the Fitter would prefer to place it.
New ContributorHi sstrell:
Thanks for your reply, but it's not the answer what I approach for.
I want to forbid Quartus Prime to use a particular resource, because I find some particular LAB delay is 10x larger than a normal LAB in Timing Analyzer. After I use chip planner for post-netlist ECO to change the LAB resource to a adjacent LAB, the problem is solved. So, I think the 10x delay LAB may be something wrong.
I appreciate it if you could kindly provide a solution for my request.
Super ContributorI don't understand how a particular LAB could be slower than any other. They are identical. Can you share your .sdc and the timing report where you're seeing this? There is some reason why the Fitter is selecting this LAB for you (super full design perhaps?) and causing the issue. The extra delay may be getting a signal to a particular physical location, not the physical resource itself. If that's the case, you need to figure out why the Fitter is doing this.
The ECO fixes it, but it might be useful going forward to understand the cause of the issue.
New ContributorHi Sstrell:
I don't understand that either, but it happens.
I provide the Chip Planner layout and Timing report here.
The utilization of my design is 27%, and I think it's not an issue for FPGA fitter.
BTW, if you know how to avoid using a specific LAB in Quartus Prime, please tell me how. Thank you.
