Forum Discussion
ak6dn
Regular Contributor
5 years agoVerilog language does not support such datatypes for synthesis. Use need to use a 16, 24, 32, 64 bit wire / register as a port that you pass the encoded floating value thru.
If you are just writing verilog (like for a testbench) you can use the real datatype which will pass floating point numbers thru ports. No synthesis, however.