How can I simulate Triple-Speed Ethernet Intel FPGA IP in Modelsim?
I have a Quartus project with a Platform Designer system where I have instantiated a Triple-Speed Ethernet Intel FPGA IP. However, I cannot compile a netlist without removing from Assignments-> Setti...
Okay, I was able to simulate the TSE MAC using Quartus 18.1 Std version targeted the Max10 10M50DA device. So as I see it, there seems to be no issues in simulating the TSE IP core.
Do you have the license required for TSE MAC IP simulation &synthesis?
When you generated the TSE MAC IP via Platform designer/Qsys, a window pops up asking if you want to generate the example design. Have you generated the example design?
If not, then I suggest you re-generate the example design. This contains the simulation data for the IP. Two folders will be generated : <ip_name>_simand <ip_name>_testbench.
Navigate to the <ip_name>_testbench folder. Here you will find another QSF (Quartus project) that will generate the complete testbenches and sim data.
Open the project named generate_sim.qsf in Quartus.
From the tools menu select TCL Scripts..
In the window that pops up, select the Generate testbench system (Verilog) and click Run. This will generate the complete testbench system with test cases for your IP that you have generated.
Invoke ModelSim, change to the testbench_verilog folder, and then to the <ip_name> folder.
Here you will find the following files :
run_<ip_name>_tb.tcl
<ip_name>_wave.do
<ip_name>_tb.v
Run the tcl file in ModelSim by issuing the following command : do <ip_name>_tb.tcl.
This will start the simulation and you can see the outputs in the waveform viewer as well as in the console output window.
New Contributor
