How can I figure out what made my Fitter (Place and Route) time balloon?

I found the problem. Should anyone else run into a similar problem, they *might* have done what I did: write VHDL code meant to infer a RAM that did *not* infer a RAM. I used the Netlist viewer to look at the components, found that the RAM was *not* considered a memory. Once I used Qsys to create a RAM and replaced my VHDL code the synthesis time went back to around ten minutes.