Forum Discussion
Honored ContributorHow can I do with this error of new version of the modelsim?
I have download and install the Quartus Prime Lite Edition (Free) with ModelSim-Altera Edition (includes Starter Edition) in it.When I use the ModelSim-Altera 10.4b (Quartus Prime 15.1) to Simulate my project,a error shows that'can't read "Startup(-L)": no such element in array'.:(It just a gate-level Simulation.When I use other computer and other version of the ModelSim-Altera,it Simulate all right:confused:.The setting is the same.The library is altera_mf_ver.And my project is very sample,a IP core of PLL for Frequency doubling,input and output.
http://www.alteraforum.com/forum/attachment.php?attachmentid=11441&stc=17 Replies
Altera_ForumIf you regenerate your PLL in 15.1, will there be any difference?
- Altera_Forum
I'd also suggest re-compiling the simulation library with the newer version of Modelsim. See the Modelsim docs for details on how to do this.
- Altera_Forum
The quartus II 15.1 just the UI is difference,others I do not feel difference.
- Altera_Forum
I have re-compiling the altera_mf_ver library,it didn't works,the problem is the same,the error message change to '# ** Error (suppressible): (vsim-10000) F:/TEST/asd.v(159): Unresolved defparam reference to 'altpll_component' in altpll_component.width_clock.
# Time: 0 ps Iteration: 0 Instance: /TEST/b2v_inst File: F:/TEST/asd.v # Error loading design' - Altera_Forum
Did you add the .sip file to your quartus project before creating the simulation? You need to generate simulation files when running the IP catalog, and add them to your quartus project before simulating. Also, create your test bench (if you need one) and add it as simulation only source.
- Altera_Forum
When I use quartus II generate the IP catalog,the quartus II will build up the verilog file,I was use that file to simulation.As the picture,the asd.v file was the IP catalog build up file. I have just simulate the clock,so I do not use the test bench in this project.
- Altera_Forum
The sip file includes other files modelsim will need to use to simulate Altera IP. Make sure you add it to your project. Remove any previously added files that are also mentioned in the project. The qip files list files needed to synthesize your FPGA configuration. The sip files list files needed for simulation. There is considerable overlap, but both are need to be added to your Quartus project. When you tell Quartus to simulate, it uses the sip files to create the modelsim project.
