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Honored Contributor
11 years agoHello,
Isn't this what you are looking for? //---------------------------------------------------------- module generate_1 ( /*AUTOARG*/ // Outputs selected_r0out, // Inputs Reset, clock_buff, mem_out, r0out_selection, rfc ); input clock_buff; input Reset; input [31:0] mem_out; input [31:0] rfc; input [4:0] r0out_selection; output [31:0] selected_r0out; wire [31:0] r0out[31:0]; assign selected_r0out = r0out[ r0out_selection[4:0]]; generate genvar i; for ( i=1; i<=32;i=i+1 ) begin : register_file register r ( // Outputs .dataout (r0out[i-1]), // Inputs .clk (clock_buff), .datain (mem_out), .enable (rfc[i-1]), .reset (Reset) /*AUTOINST*/); end endgenerate endmodule // generate_1 // ----------------------------------------------------------------------------------------------- //------------------------------------------------------------------------------------------------ module register (/*AUTOARG*/ // Outputs dataout, // Inputs clk, datain, enable, reset ); input clk; input reset; input enable; input [31:0] datain; output [31:0] dataout; reg [31:0] dataout; always @ ( posedge clk or posedge reset ) begin if ( reset ) begin dataout <= 32'h0; end else if ( enable ) begin dataout <= datain; end end // always @ ( posedge clk or posedge reset ) endmodule // register // Have a Joyful Day. //------------------------------------------------------- Cheers, Bhaumik