How avoid registers or wires are removed (by the optimizator) for creating small delays?

I'm new with the quartus software and now i'm fighting with a very simple problem.

I need to create some clocks skews adding some ports as little delays, but i'm not able to to avoid the optimizer remove all my addictive ports , so i'm not able to add any timing shifts.

How can I control that? i tried unckeck all optimizations available, but always all wires and registers are removed.

For example to be able to use this module:

// ****************

module my_delay_line(s_in ,s_out);
parameter n=20;
genvar i;
input s_in;
output s_out;
wire [n-1:0] delay;
assign s_out=delay[n-1];
assign delay[0] = ~s_in;
generate
for (i=0; i<n-1; i=i+1)
begin: generate_delay
assign delay [i+1] = ~delay [i ];
end
endgenerate
endmodule

// ********************

Thank you.