How are shift registers implemented.

The Altera documents recommend using shift registers for convolution image processing tasks like in this example: https://www.altera.com/support/support-resources/design-examples/design-software/opencl/sobel-filter.html

What surprised me a bit is how little the logic utilization, and usage of any other resource in the quartus report, increases with the size of the shift register. I've used shift registers that hold around 6000 values. As long as I only access a few of them, the resource usage increases very little. The thing is, it still needs to hold all the values even if I only use the last one, as at some point any given value will be shifted into the last position.

I'm wondering how these shift registers are implemented in the hardware so that it can hold 6000 values with ease. Is there some special primitive for FIFOs in the FPGA. If yes, why is the quartus report not showing it?